1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an electrostatic discharge protective circuit.
2. Description of the Related Art
Electrostatic discharge (ESD) is one of the major ways for an integrated circuit (IC) to be damaged in an IC fabrication process. This is especially true for fabrication of a deep sub-micron IC. In order to overcome the problems caused by static electricity, an ESD protective circuit is incorporated onto the input/output (I/O) pads of a complementary metal-oxide-semiconductor (CMOS) IC through an on-chip method.
Since the gate oxide layer becomes thinner as the line width of the semiconductor fabrication process is downsized, the breakdown voltage of the gate oxide layer approaches or is lower than that of the source/drain junction. Hence, the protection provided by the ESD protective circuit becomes less effective. Additionally, design of the inner circuit often follows minimum design rules. Because the inner circuit is not appropriately designed (such as enough spaces for contact-to-diffusion edge and contact-to-gate electrode edge) for resisting the large ESD transient current, the wafer is easily damaged by ESD in highly integrated circuits. Therefore, ESD is one of the major reasons leading to failure in deep sub-micron integrated circuits.
FIG. 1A is a circuit diagram for a conventional ESD protective circuit. As shown in FIG. 1A, in order to protect the internal circuit 10, the ESD current imported through an input port INP is discharged through an NMOS transistor N1 to a ground V.sub.ss. FIG. 1B is a schematic circuit diagram of another conventional ESD protective circuit. As shown in FIG. 1B, in order to protect the internal circuit 10, the ESD current can be discharged not only through an NMOS transistor N1 to the ground V.sub.ss but also through a PMOS transistor P1 to a voltage source V.sub.DD.
FIGS. 2A through 2D are schematic, cross-sectional views of the conventional process for manufacturing an ESD protective circuit.
As shown in FIG. 2A, an isolation structure 22 is formed on a substrate 20 to define an inner circuit region 24 and an ESD protective circuit region 26. Transistors 28 and 30 are respectively formed on the inner circuit region 24 and the ESD protective circuit region 26. The transistor 28 comprises a gate oxide layer 32a on the substrate 20, a gate electrode 34a on the gate oxide layer 32a, a spacer 36a on the sidewall of the gate electrode 34a and the gate oxide layer 32a and a source/drain region 38a having a lightly-doped drain (LDD) structure in a portion of the substrate 20 exposed by the gate electrode 34a. The transistor 30 comprises a gate oxide layer 32b on the substrate 20, a gate electrode 34b on the gate oxide layer 32b, a spacer 36b on the sidewall of the gate electrode 34b and the gate oxide layer 32b and a source/drain region 38b having an LDD structure in a portion of the substrate 20 exposed by the gate electrode 34b.
As shown in FIG. 2B, a salicide block (SAB) layer 40 is formed to cover the ESD protective circuit region 26.
As shown in FIG. 2C, a salicide process is performed to form silicide layers 42 and 44 on the gate electrode layer 34a and the source/drain region 38a, respectively.
As shown in FIG. 2D, the SAB layer 40 is removed. A dielectric layer 46 is formed to cover both inner circuit region 24 and the ESD protective circuit region 26. An anisotropic etching is performed to remove a portion of the dielectric layer 46 and to exposes a portion of the silicide layer 44 and a portion of the source/drain region 38b.
The inner circuit and the ESD protective circuit are formed at the same time without performing any additional processes. However, since the silicide layer is not formed on the gate electrode 34b of the transistor 30 before the formation of the SAB layer is performed, the resistance of the gate electrode and the propagation delay are increased.
Moreover, if a portion of the ESD protective circuit region is covered by a SAB layer. the contact-to-gale electrode edge rule will be reduced. For example, as shown in FIG. 3, the original contact 50-to-gate electrode 52 edge rule is D1+D2+D3. After only a portion of the ESD protective circuit region is covered by the SAB layer 54, since the silicide layer may formed on portions of the source/drain region 56 exposed by the contact 50, the SAB layer 54 and the gate electrode 52, the contact 50-to-gate electrode 52 edge rule becomes only D2. Therefore, the current dissipation path is reduced and the protective efficacy is lessened.